1. Field of the Invention
This invention generally relates to system-on-chip (SoC) processor core management and, more particularly, to a system and method for using a hardware core and dedicated communication interfaces to monitor and control SoC processor core voltages and operating frequencies.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a processor indirectly connected to temperature sensors (prior art). Conventionally, a microprocessor 100 communicates directly with the fan controller 102 via the platform environment control interface (PECI) bus. However, the CPU sensor 104, whether mounted on or near the CPU 100, must relay its readings via the system management bus (SMBUS) and SMBUS controller 106, the I/O controller hub (ICH) or southbridge 108, the digital media interface (DMI), the memory controller (northbridge) 110, and the front side bus (FSB). Likewise, a sensor (TS) 112 mounted on the memory 114, or a sensor 116 mounted on the board near the memory takes the same indirect path. This indirect path requires communication between different subsystems, making the monitoring process relatively complex and slow. With respect to the processor 100, the temperature monitoring and fan control processes are managed by operating system (OS) software, again making these processes relatively complex and slow, as well as interrupting the processor from completing other tasks. The CPU temperature can also be regulated by controlling the processor operating frequency. Conventionally however, the frequency of operation is changed through manually intervention to modify the dc supply voltage or through a software mechanism. Manual intervention and software mechanisms are both relatively cumbersome.
Conventionally, there is only one core voltage source that feeds voltage to all the processor cores inside a SoC. Reducing the voltage for one core results in a voltage reduction for all the cores, and degrades the performance of all the cores. A disadvantage of this architecture is that if there is a voltage failure for the core voltage, all the cores are affected. Similarly, a core that develops a physical problem may affect all the other cores indirectly through the voltage bus.
It would be advantageous if the processor core operating voltages of an SoC could be individually managed by a dedicated management core (hardware block).